1. Field of the Invention
This invention relates to a synchronization signal detector for detecting synchronization signals or frame synchronization signals recorded on a recording medium, a method for detecting synchronization signals, and a demodulator for demodulating the data stored on a recording medium.
2. Description of the Prior Art
On a recording medium, such as an optical disc, magnetic disc, or a magneto-optical disc, synchronization signals (frame synchronization signals, synchronization patterns, sync patterns) are usually recorded so as to be employed later for signal reproduction. In a conventional arrangement for detecting these synchronization signals, as shown in FIG. 6, a number of D type (data type) flip-flops 65.sub.0 to 65.sub.M corresponding to the length of the pattern of the synchronization signal are arrayed. That is, a number of the D flip-flops equal to the bit length of the synchronization signal are arrayed. Outputs of the D-flip-flops, in the form of a suitable pattern corresponding to the synchronization pattern, are ANDed by an AND gate 68 to decide whether or not the input signal is the synchronization signal.
RF signals produced by an optical pickup from reading pits or from signal recording regions on a recording media, such as an optical disc or a magneto-optical disc, or RF signals produced by a magnetic head reading the pits or the recording regions on a media surface, are supplied to an input terminal such as input terminal 61 in FIG. 6.
These RF signals are supplied to a binary value detector 62, operated on the basis of clock signals supplied thereto from a terminal 64, for translating the input RF signals into binary-valued signals based on predetermined signal levels as threshold levels.
The output binary-valued signals from the binary-valued signal detector 62 are transmitted to a number of series-connected D flip-flops 65.sub.0 to 65.sub.M corresponding to the length M of the pattern of the synchronization signal to be detected. From these D-flip-flops 65.sub.0 to 65.sub.M, operated by the clock signals, non-inverted output signals or inverted output signals, corresponding to the pattern of the synchronization signal prescribed by the relevant format, are output, depending on the "H" active or "L" active state of the circuitry as selected in accordance with the synchronization pattern prescribed by the format.
The non-inverted output or the inverted output from the D flip-flops 65.sub.0 to 65.sub.M are supplied to the AND gate 68. The AND gate 68 takes a logical sum of the non-inverted or inverted outputs to output a signal indicating detection of the synchronization signal when the pattern of the binary-valued signals corresponding to the input RF signals becomes a pattern peculiar to the synchronization signal. This peculiar pattern is a pattern not appearing in any other data. The output signal from the AND gate 68 is output as a synchronization signal detection output at an output terminal 69.
It is noted that, if the original signal is in the form of non-return-to-zero inverted (NRZI) signals in which the signal state is inverted only when the bit information data is "1", and the synchronization pattern is in the form of non-return-to-zero (NRZ) signals such that the signal state is inverted at a boundary between the bit information data, an additional circuit similar to that shown in FIG. 6 needs to be provided side-by-side. An output of the additional circuit and an output of the circuit shown in FIG. 6 are ORed by an OR gate, not shown, to produce an OR output as a synchronization signal detection output.
In the above-described conventional arrangement for detecting the synchronization signals, plural synchronization signals of different patterns may be detected by arbitrarily combining outputs of the D flip-flops in conformity to various patterns peculiar to the synchronization signals.
However, if, with the above-described conventional arrangement for detecting the synchronization signals, the pattern length of the synchronization signal is increased, it becomes necessary to array an increased number of D flip-flops, leading to an increased circuit scale.
With the above-described arrangement, it is necessary to provide an AND gate having a number of inputs corresponding to the bit length of the synchronization signal pattern, leading to a further increased circuit size. If the AND gate is divided into plural AND gate elements for reducing the circuit size, delay times of the AND gate elements and associated circuit devices are accumulated to lower the speed demanded of the circuit elements.
If, in case of division of the AND gate, a D flip-flop, for example, is annexed as a latch for maintenance of the operating speed, delay times are similarly produced for synchronization signal detection in the same manner as described above.